The inventive concepts described herein relate to supply voltage scaling techniques, and more particularly, to voltage level shifters and systems implementing voltage level shifters.
The most effective low-power technique for electronic systems is supply voltage scaling. However, System on Chip (SOC)/Central Processing Unit (CPU) supply voltage scaling may be limited in some designs by the minimum voltage requirements in Static Random Access Memory (SRAM) devices (i.e., SRAM Vmin). This may particularly be the case with high-density SRAM bit cells. In order to overcome SRAM Vmin limitations and still produce a low-power device, a dual-supply design (DSD) technique has been implemented, in which a first conditionally lower voltage domain (VDD1 or VDDL (Logic VDD)) is used for logic circuits, and a second, higher voltage domain (VDD2 or VDDS (SRAM VDD)) is used for the SRAM cells. This DSD technique requires a transition (i.e., level shifting) from the lower voltage domain to the higher voltage domain. In contrast, the transition in the other direction (from the higher voltage domain to the lower voltage domain) can occur transparently without an explicit level shifter circuit.
A conventional method for transitioning from the lower-voltage logic section to the higher-voltage SRAM macro is to insert explicit voltage level shifters into the circuit at the SRAM input boundary. Unfortunately, this method has two primary disadvantages. First, the insertion of explicit voltage level shifters increases the signal delay for signals transitioning from the lower-voltage domain to the higher-voltage domain. The second disadvantage is the increased power requirements for the SRAM peripheral circuits located in the higher-voltage domain rather than the lower-voltage domain.
In an alternative approach, illustrated in FIG. 1 for example, a DSD technique may use a simple inverter level-shifter to transition between the lower-voltage (VDD1) and the higher-voltage (VDD2) domains. In this approach, most of the peripheral circuits as well as the bit lines can be arranged in the lower-voltage (VDD1) domain for power saving. FIG. 2 is a schematic signal diagram illustrating various signals passing through the inverters of FIG. 1. As illustrated in FIG. 2, this inverter level-shifter design can transition a signal voltage from the lower-voltage (VDD1) level to the higher-voltage (VDD2) level. Unfortunately, however, in this technique, the amount of logic VDD scaling may be limited due to problems with leakage current.
More specifically, referring now to FIG. 1A, the lower-voltage (VDDL) level is typically limited to at most around 200 mV below the higher-voltage (VDDH) level. Otherwise, leakage current can undesirably increase because the PMOS transistor 12 arranged at the voltage domain boundary may be weakly turned on when the input voltage (VOH) from the lower-voltage (VDDL) domain is high, but still less than the higher-voltage (VDDH) level (i.e., not high enough to completely turn off the PMOS transistor 12). In other words, if the difference between voltages in the two domains (VDDH and VDDL) is too great, the PMOS transistor 12 in the inverter i3 arranged at the boundary between the two voltage domains will not shut-off completely and a leakage current ILeak will flow through the transistor 12. This power loss can dramatically reduce the power saving benefits of the DSD circuit. It would therefore be desirable to have a voltage-level shifter design that overcomes these drawbacks.